MAX5952CUAX+【PDF 23/50 页】IC PSE CNTRLR FOR POE 36-SSOP

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High-Power, Quad, PSE Controller

for Power-Over-Ethernet

______________________________________________________________________________________ 23

Serial Addressing

Each transmission consists of a START condition (Figure

6) sent by a master, followed by the MAX5952 7-bit

slave address plus R/W bit, a register address byte, one

or more data bytes, and finally a STOP condition.

START and STOP Conditions

Both SCL and SDA remain high when the interface is

not busy. A master signals the beginning of a transmis-

sion with a START (S) condition by transitioning SDA

from high to low while SCL is high. When the master fin-

ishes communicating with the slave, the master issues

a STOP (P) condition by transitioning SDA from low to

high while SCL is high. The STOP condition frees the

bus for another transmission.

Bit Transfer

Each clock pulse transfers one data bit (Figure 7). The

data on SDA must remain stable while SCL is high.

Acknowledge

The acknowledge bit is a clocked 9th bit (Figure 8) that

the recipient uses to handshake receipt of each byte of

data. Thus each byte effectively transferred requires 9

bits. The master generates the 9th clock pulse, and the

recipient pulls down SDA (or the SDAOUT in the 3-wire

interface) during the acknowledge clock pulse, so that

the SDA line is stable low during the high period of the

clock pulse. When the master transmits to the MAX5952,

the MAX5952 generates the acknowledge bit. When the

MAX5952 transmits to the master, the master generates

the acknowledge bit.

Figure 6. START and STOP Conditions

START

STOP

SDA/

SDAIN

SCL

Figure 7. Bit Transfer

SDA

SCL

DATA LINE STABLE;

DATA VALID

CHANGE OF

DATA ALLOWED

Figure 8. Acknowledge

SCL

SDA

BY TRANSMITTER

CLOCK PULSE FOR ACKNOWLEDGEMENT

START CONDITION

SDA

BY RECEIVER

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